Programmable Logic Project of the Month

Here's where I'll try to show you something we've done with PLDs this month. Always quick and dirty, and the month is plus or minus a few days, OK? These circuits are easy to try with our PLD prototyping kits. If you need help getting started with PLDs check out our tutorials at http://tutor.al-williams.com. Want to discuss the project of the month? Check out http://groups.yahoo.com/group/awcpld.

This Month's News

As you can see, the Programmable Logic Project of the Month is on hiatus.

February 2003

Looking for the Stamp Project of the Month?

PWM

PWM is a well-known method to control motor speed or light brightness with microprocessors. The idea is to toggle the duty cycle of a pulse output. If the average duty cycle is, say, 50%, the motor will run at half speed (or the light will be at half brightness).

One easy way to generate 8-bit PWM is to use the following algorithm:

1. Add the desired duty cycle (from 0 to 255) to an accumulator.

2. Output the carry (the 9th bit) as the PWM output.

3. Go back to step 1.

This is pretty easy to write in Verilog (or even draw in a schematic).

Note: The examples below were done on a XC9500. ISE takes out the initial statements and also resets all the flip flops on reset. If you are targeting another device you may need to comment out the initial statements and provide an explicit reset.

Here's a PWM module:

module PWM(DC,CLK,Q,RESET);
input [7:0] DC;  // duty cycle input
input CLK;
input RESET;
output Q;
reg [8:0] acc;   // accumulator has one more bit than the duty cycle
assign Q=acc[8];  // output is the 8th bit

initial acc=0;   // for simulation only
always @(posedge CLK) 
begin
if (RESET) acc=0;
acc=acc[7:0]+DC;   // only add with 8 bits.
end
endmodule

Of course, you could make the width a parameter by replacing the 7s and 8s in the listing with a parameter expression (like BITS-1 and BITS). If you need a refresher on parameters, be sure to read our Verilog tutorial at http://tutor.al-williams.com.

I tested the above module on a PBX-84 with a 50MHz clock:

module PWMMain(DC,CLK,Q);
input [7:0] DC;
input CLK;
output Q;
wire CLKO;
// synthesis attribute LOC clk "P9"
// synthesis attribute LOC Q "P1"
// synthesis attribute LOC DC "P11","P10","P7","P6","P5","P4","P3","P2"

clkdiv div(CLK,CLKO,0);
PWM pwm(DC,CLKO,Q,0);


endmodule

A 50MHz clock makes the LED blink to fast, so I added the clkdiv module to divide the clock down:

module clkdiv(CLKIN,CLKOUT,RESET);
input CLKIN;
output CLKOUT;
input RESET;
wire iclk;
parameter BITS=13;
reg [BITS-1:0] COUNT;
initial COUNT=0;
assign CLKOUT=COUNT[BITS-1];
BUFG clkbuf(iclk,CLKIN);
always @(posedge iclk)
begin
if (RESET) COUNT=0;
COUNT = COUNT + 1;
end
endmodule

By the way, experiments like this are simple with a small adapter board that plugs into the PBX-84. This board has 8 switches with pullup's, 8 5V LEDs, and a 50MHz clock. We may make these boards available next year if there is a demand -- drop me a line if you are interested in them.

Webpack 5.1 Note

By the way, I upgraded to the latest Webpack during this project. For some reason it kept giving me an error during fitting. I tried starting a new project and just moving the Verilog code, but I kept getting the error. The file the error was complaining about was c:\xilinx51\data\projnav\scripts\_cpldfitrun.tcl.

I'm not sure why this kept happening. As an expedient, I simply commented out these three lines (the # lines):

if { [string equal $p_DevFamily xc9500] } {
# if { !$xcpldFitDesFastConnectUIM } {
# lappend Options "-nouim"
# }
switch -- $xcpldFitDesLocalFbk {

This apparently has something to do with the Fast Connect option, but I couldn't find any other way to get that error to stop. I'm not the only one to notice -- here's a newsgroup thread on the subject.

About Printing

Many of you like to print the project of the month out for your personal use and that's fine with us. However, when you print, you may find that the page is too wide to print correctly on your printer. This is how the browser handles wide pages and is not something we do deliberately to prevent printing. First, many printers have a "scale to fit page" option. That will usually work pretty well. The other alternative is to print in landscape mode! Usually the wider page will fit the project with no troubles. We do ask that you not post the projects to the Web or otherwise distribute them, but personal copies for your own use are fine!

Here's another tip sent in by Dustin Christopherson:

I sure love your site and your information is very helpful. I noticed on your Basic Stamp Circuit of the Month it has a section about printing the document. Just thought I would let you know that one of the ways I find that works best with printing such a page is to select the text and leave the graphics on the left unselected. Then, when you go to print the document, select the "print selection" option. This way, none of the navigational buttons for the web site are printed and you don't have a big margin on the left and none of the text is cut off. Also, doing it this way will allow you to print portrait. I just printed the Basic Stamp Circuit of the Month using this technique and it looks great!

Thanks Dustin!

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